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<title>MTB CAT1 Peripheral driver library: TX Interrupt Statuses</title>
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<a href="#define-members">Macros</a>  </div>
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<div class="title">TX Interrupt Statuses<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a> &raquo; <a class="el" href="group__group__scb__common.html">Common</a> &raquo; <a class="el" href="group__group__scb__common__macros.html">Macros</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga4a3246f84b4c56a8c570b9a622e2af72"><td class="memItemLeft" align="right" valign="top"><a id="ga4a3246f84b4c56a8c570b9a622e2af72"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__common__macros__tx__intr.html#ga4a3246f84b4c56a8c570b9a622e2af72">CY_SCB_TX_INTR_LEVEL</a>&#160;&#160;&#160;SCB_INTR_TX_TRIGGER_Msk</td></tr>
<tr class="memdesc:ga4a3246f84b4c56a8c570b9a622e2af72"><td class="mdescLeft">&#160;</td><td class="mdescRight">The number of data elements in the TX FIFO is less than the value of the TX FIFO level. <br /></td></tr>
<tr class="separator:ga4a3246f84b4c56a8c570b9a622e2af72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga864a9f7ac3a3c72b82b9ca3d18d492a6"><td class="memItemLeft" align="right" valign="top"><a id="ga864a9f7ac3a3c72b82b9ca3d18d492a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__common__macros__tx__intr.html#ga864a9f7ac3a3c72b82b9ca3d18d492a6">CY_SCB_TX_INTR_NOT_FULL</a>&#160;&#160;&#160;SCB_INTR_TX_NOT_FULL_Msk</td></tr>
<tr class="memdesc:ga864a9f7ac3a3c72b82b9ca3d18d492a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TX FIFO is not full. <br /></td></tr>
<tr class="separator:ga864a9f7ac3a3c72b82b9ca3d18d492a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga24723ba8c328d957e1713cb8bc888502"><td class="memItemLeft" align="right" valign="top"><a id="ga24723ba8c328d957e1713cb8bc888502"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__common__macros__tx__intr.html#ga24723ba8c328d957e1713cb8bc888502">CY_SCB_TX_INTR_EMPTY</a>&#160;&#160;&#160;SCB_INTR_TX_EMPTY_Msk</td></tr>
<tr class="memdesc:ga24723ba8c328d957e1713cb8bc888502"><td class="mdescLeft">&#160;</td><td class="mdescRight">The TX FIFO is empty. <br /></td></tr>
<tr class="separator:ga24723ba8c328d957e1713cb8bc888502"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1574ab8c43b9b2e20c62527dd56f3f6"><td class="memItemLeft" align="right" valign="top"><a id="gad1574ab8c43b9b2e20c62527dd56f3f6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__common__macros__tx__intr.html#gad1574ab8c43b9b2e20c62527dd56f3f6">CY_SCB_TX_INTR_OVERFLOW</a>&#160;&#160;&#160;SCB_INTR_TX_OVERFLOW_Msk</td></tr>
<tr class="memdesc:gad1574ab8c43b9b2e20c62527dd56f3f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">An attempt to write to a full TX FIFO. <br /></td></tr>
<tr class="separator:gad1574ab8c43b9b2e20c62527dd56f3f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafc4090b887bf3aebb4a8eaf917754897"><td class="memItemLeft" align="right" valign="top"><a id="gafc4090b887bf3aebb4a8eaf917754897"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__common__macros__tx__intr.html#gafc4090b887bf3aebb4a8eaf917754897">CY_SCB_TX_INTR_UNDERFLOW</a>&#160;&#160;&#160;SCB_INTR_TX_UNDERFLOW_Msk</td></tr>
<tr class="memdesc:gafc4090b887bf3aebb4a8eaf917754897"><td class="mdescLeft">&#160;</td><td class="mdescRight">An attempt to read from an empty TX FIFO. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__common__macros__tx__intr.html#ga3a643407857952a829f132e8c31c13c7">CY_SCB_TX_INTR_UART_DONE</a>&#160;&#160;&#160;SCB_INTR_TX_UART_DONE_Msk</td></tr>
<tr class="memdesc:ga3a643407857952a829f132e8c31c13c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">The UART transfer is complete: all data elements from the TX FIFO are sent. <br /></td></tr>
<tr class="separator:ga3a643407857952a829f132e8c31c13c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__common__macros__tx__intr.html#ga6810ac0a6f6a66418be8086dd2faa4d8">CY_SCB_TX_INTR_UART_NACK</a>&#160;&#160;&#160;SCB_INTR_TX_UART_NACK_Msk</td></tr>
<tr class="memdesc:ga6810ac0a6f6a66418be8086dd2faa4d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">SmartCard only: UART received a NACK. <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__common__macros__tx__intr.html#ga789d149dbec0497816bc07ed3a54b5dc">CY_SCB_TX_INTR_UART_ARB_LOST</a>&#160;&#160;&#160;SCB_INTR_TX_UART_ARB_LOST_Msk</td></tr>
<tr class="memdesc:ga789d149dbec0497816bc07ed3a54b5dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">SmartCard only: the value on the TX line of the UART does not match the value on the RX line. <br /></td></tr>
<tr class="separator:ga789d149dbec0497816bc07ed3a54b5dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
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